fpga4fun.com

HI,
I tried to compile the Ethernet UDP project on Xilinx 9.1i,application version J0.30. The PC is a Windows Vista professional desktop.

The design synthesizes no problem. But during the implementation process, it hits a snag during the NGD build. THe tool barfs and throws this error-

ERROR:NgdBuild:604 - logical block 'ram' with type 'ram8x512' could not be
resolved. A pin name misspelling can cause this, a missing edif or ngc file,
or the misspelling of a type name. Symbol 'ram8x512' is not supported in
target 'spartan3e'.
I searched this forum and the WWW and did not see anybody having problems with the Ethernet project,at least building it. Could somebody help me figure out as to what is going on. I am do

Thanks,
duddface

Did you enable the "define" in the beginning of the verilog file?

I did so now and the design builds. My bad, have to make sure to go through every line of a source before I run around like crazy.


Thanks