Start of Manchester Decoding

Start of Manchester Decoding

Postby damc4 » Tue Oct 07, 2003 4:58 pm

Hi Jean,

I just read your homepage about oversampling to do Manchester decoding and one question arised I couldn't find an answer.
If I get this Manchester coded data stream into my FPGA: ...000000000000100110011001... (these should be the transitions of the signal)
How do I find out if I am in the middle of the first bit? E.g. is this partitioning correct (...00000000000 01 00110011001...) or this one (...000000000000 10 0110011001...) for the first bit?

DAMC
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Postby fpga4fun » Tue Oct 07, 2003 7:52 pm

The trick is that there is always a transition in the middle of logic bits.

They start transmission on purpose with a sequence (preamble) where the transitions are only in the middle of logic bits. So the decode logic can't get it wrong.

The preamble is something like "0101010101" (before Manchester encoding). After Manchester encoding that gives "10011001100110011001". So even if the receiver misses a few bits, it should synchronize where the transitions are and decide these are the middle bits.

Jean
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Postby Stijena » Tue Jan 27, 2004 11:00 am

Does it mean that we can also revert the positive and negative lines at the input diff pins
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Postby fpga4fun » Tue Jan 27, 2004 6:08 pm

The input diff doesn't care about the polarity, and the receiver is usually smart enough to detect the polarity of the incoming bit stream by looking at the preamble.
I don't know if it's part of the IEEE802.3 standard though.
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Postby Stijena » Tue Jan 27, 2004 6:26 pm

Jan, when I mentioned reversing the input lines I was thinking of the manchester decoder at Fpga4Fun, Is this one smart enough?

And also did You think of making something like "Xilinx Pluto" because there exist at least two "tribes" in the FPGA world (A and X)

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Postby Stijena » Tue Jan 27, 2004 6:29 pm

PS: some of new low cost chips (both altera and xilinx) also have differential I/Os so it would ease building some of the projects (especially ethernet phy ). Did You try it already?
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Postby fpga4fun » Tue Jan 27, 2004 6:48 pm

My Manchester decoder isn't smart enough... but it would easy to add... just detect the polarity of the last bit of the preamble.
I wanted to keep the published code as simple as possible, so I didn't include that.

Yes, a Xilinx board is in the works.
Using differential IOs might be possible, haven't looked into that yet.
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