fpga4fun.com

Hi Jean,

10BASE-T FPGA is very interesting.

Are you able to advise how can I send out the packet faster? I have tried to modify the following codes but seems like my pc can't detect or discarded the packets if the count value is reduced.

//////////////////////////////////////////////////////////////////////
// sends a packet roughly every second
reg [23:0] counter; always @(posedge clk20) counter<=counter+1;
reg StartSending; always @(posedge clk20) StartSending<=&counter;

If I need to send out the packet in ~1ms intervals, how should I do it. Please help to advise.

regards,
Dave

Did you try 10ms intervals?

Hi, many thanks for your reply. I have tried the 10ms interval but getting no response from the Wireshark or the UDP tester programs:

Below are my modification done to your codes for the counter portion:

reg [17:0] counter = 0;
reg StartSending = 1'b0 ;
reg [31:0]PacketID = 32'd0;

always @(posedge clk20)
begin
counter <= counter + 1;
if(counter == 18'd200000)
begin
StartSending <= 1'b1;
counter <= 0;
PacketID <= PacketID + 1;
end
else
StartSending <= 1'b0;
end

Try 100ms then.
If that doesn't work, maybe there is a mistake in your code, go back to the original code and reduce the counter width instead.

Hi, still getting no response for the interval of 100ms. I have put back the orginal coding and changed the counter width to [20:0] so that to count about 105ms as shown in the following codes:


reg [20:0] counter; always @(posedge clk20) counter<=counter+1;
reg StartSending; always @(posedge clk20) StartSending<=&counter;


If for the 1ms interval, the LED on my 10/100 Switch in constanly ON. It is because of some hardware issue that I need to put a isolation transformer between the FPGA and the LAN port? or the signal is actually to my switch is very noisy?

Thanks for your reply.

Does 105ms work?

1ms is very fast, I'm not surprised that the LED is constantly on.

Hi, I have modified the code such that it the board will transmit the packet in 105ms seconds. LED is always light up on my LAN switch, but there is still no response from the test program (Wireshark/UDP).

Have you try to send out the packet at this rate before, e.g 1ms interval?

I have used the SignalTap to look at the output waveform, it look ok and there is no overlapping of packets when carried a very large payload in 1ms interval.

Could the problem is due to there is no flow control implemented in the design?

Thanks.

Hi, is the board sending the packet too fast for even the fastest receivers? What I'm trying to do here is to send out packet in 1ms with the maximum allowable payload.

I just tried the 105ms modification and I receive the packets fine...

reg [20:0] counter; always @(posedge clkTx) counter<=counter+1;
reg StartSending; always @(posedge clkTx) StartSending<=&counter;

Try to get the latest startup kit, maybe you are not using the latest code.

Hi, is it possible for you to send me the codes for the Ethernet project? I'm not using the kit from your side at this moment. Therefore, I dont have access to the codes.

Thanks.

The code I'm using is copyrighted and is available only with KNJN boards.

Hi All,

Anyone ever try to modify the codes post in the webpage: "10BASE-T FPGA interface part 0 - A recipe to send Ethernet traffic" and able to send out the ethernet packet in much faster rate e.g less than 100ms?

Thanks.

Hi,
I think the problem with packet speed above a certain rate has to do with NLP.

I did some playing with the ethernet transmitter code (TENBASET_TxD).
I tried to increase the number of packets sent per second, by changing the amount of bits in:

reg [23:0] counter; always @(posedge clk20) counter<=counter+1;

E.g. change 23 into 18.
This works fine.
However, if the packet repeat comes above the linkpulse repeat (change 23 into 17 or lower) the link is lost and no packets are received anymore.

As far as I understand from the standard, if the gap between packets is below the link repat of 16ms +/- 8 ms no NPL is required. This is also what the TENBASET_TxD code is doing.

TENBASET_TxD is syntehsized and loaded in a CPLD. Connected via switch to PC, on which wireshark runs.
The led on the switch is off above the mentioned packet speed, and also wireshark doesn't receive anything anymore.

Maybe the designer of this code can give a reaction?


Rob Alblas.

Hi Rob,

I think the code post in the web gave us thr most simplified ethernet module for sending out data and I really impress the by the programmer.

In my opinion, this code can only be a good reference. If higher packet rate need to be sent out, the best is to involve the design with interfacing a PHY chip.

regards,
David

Hi, David.
Still I am wondering: Why doesn't it work with higher speeds? I did have a look at the standard for 10Mb (IEEE802.3, or so) and as far as I understand it should work without NLP, if the gap between packets is small enough (i.e., < 8ms).
Also, the Verilog code isn't made for just 1 speed; it contains a mechanism to suppress NLP at higher speeds.
NLP interval is 16ms +/- 8ms, so the rate may vary a lot. I did increase NLP with a factor 2, and was then able to double the packet rate, but exactly at the rate where NLP's dissappear transmission fails again.
Of course for 'real' applications it is better to use a PHY with transformers etc., but isn't this a learning project? I still would like to know why higher packet rates don't work.

Rob.

Hi,

I think you need to send some NLPs before the UDP data packets so that the link is established.

I muxed two modules: one "slow module" which sends data and NLPs and another "fast module" which sends only data packets. After sending packets and NLPs with the slow module also the faster one (about 1 ms interval) works fine.

Hi, Guy.
That solves exactly my problem!
I did add an extra input on the ethtest.v, and changed the line:

reg [23:0] counter; always @(posedge clk20) counter<=counter+1;

into:

reg [23:0] counter; always @(posedge clk20) if (hsp==1 && ~&counter && counter[10]==1) counter<=24'hFFFFFF; else counter<=counter+1;

Now, if hsp='1' pakket speed is 100 us or so, no link pulses.
Disconnect and then reconnect ethernet, no transmission.
Now make hsp '0', going to low speed + NLP's ==> transmission again. Then make hsp '1', and transmission switches to high speed.

Thanks a lot,
Rob Alblas.