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I'm using the XYLO-L board XC3S500E PQ208

I've generated the .bin file for the Ethernet UDP Sample project,
and loaded it onto the Spartan 3E FPGA board. I have an ethernet
crossover cable connected from the PC directly to the RJ-45 Jack.
Under Windows XP the network connection is set to use a
static IP. The IP's are set and physical addresses also.
There is no router/hub in between the PC and the board.
FPGA IP: 192.168.2.17 MAC address: 00-12-34-56-78-90
PC Ethernet IP: 192.168.2.36
PROBLEM: Windows XP says the Ethernet cable is not connected.

The FPGA is configured to run at 24MHz as required.

I'm powering the board via the USB cable, I've got a heartbeat
running on the ARM7 outputting to the ARM7 LEDs, and I am positive
the verilog is running on the FPGA, but the FPGA LED lights are not
pulsing as expected according to the UDP project verilog code.
So it appears the UDP project verilog is not behaving as expected.
With a slight change to the verilog, I was able to turn an LED to
permanently on, so there is no PIN assignment problem.

I've got a wireless card also, and am connected to my WAN
using a separate IP address and separate MAC address. (192.168.1.107)
I wasn't able to add the ARP entry to the correct network connection,
since it didn't establish a connection. Right now there is NO ARP entry
for the FPGA, for that reason.

I looked into the modules and libraries for ISE, it appears the
RAMB4_Sm_Sn library is not available for the Spartan 3 series???
The sample code refers to RAMB4_8_8.

On the other hand the RAMB16_Sm_Sn library is available for the
Spartan 3E series, BUT I have absolutely no clue how to convert the
code and not even sure if that is the problem.

Please, any help will be appreciated!! Thanks!

Give me a few days, I'll try to give you a few idea of things to try.

Ok, in a few days is good.

I also just now, commented out the reference to the RAMB4_S8_S8, and
just set the TxData to a fixed value (eg. 8'd96) But still had no LEDs light up
for transmitting.

Also I tried another thing, I connected the board to a HUB with a straight
through Ethernet cable, and re-adjusted all of the IP / Address settings
appropriately, but still the HUB did not sense a connection from the board.

I'm starting to suspect that the RJ-45 jack is not sending any signals, but
I'm not sure how to go about testing that.

Another suspect in the code is the DCM_SP DCM_CLK20 that is suppose
to generate a 20Mhz clock pulse for transmit. But when I monitor the
posedge of that clock with an LED, it appears the CLK20 pulses are not
being generated.

Hope that leads to a more direct problem that needs to be solved.

Thanks again!!

I just figured it out! The sample project code has the DCM reset input always low 1'b0, but since the Xylo-L has the clock changed from 12MHz to 24MHz from the EEPROM sometime near startup of the board, the reset needs to be high for this initial period, and then brought low only after the input clock has stabilized.

Adding this initial reset high delay fixed the DCM timer output to tick instead of remaining high always.

WHEW!! Feels good to see that little LED flashing after struggling over the entire weekend!

Ciao for now,
Sam

Ha, didn't know you were using an EEPROM to change the clock to 24MHz.
That would explain it if the FPGA wakes up faster than the FX2 reads from the EEPROM.

Yeah, so that is going to be a problem for anyone using the
Xylo-L board, since it defaults to 12Mhz and uses EEPROM to
change to 24Mhz.

Maybe the sample UDP / HDL code for the FPGA Ethernet
project needs a slight patch to assert RST (high) for some
setup time ?

Would save others the same fate.

I guess an elegant solution would be to use one of unused IO of the FX2 to create a reset (for example PA0 which is connected to pin 162 of the FPGA). The code that sets the FX2 clock in the EEPROM would need to be updated to toggle the IO once the FX2 clock is switched.

So besides this DCM problem, the Ethernet works good?

Yes ethernet UDP is working now

I'll have to figure out how to stop losing UDP packets, and figure out how to use the RAM next.

The RAM RAMB4_8_8 should work (even if it is not native for Spartan-3E, it is promoted).

What is going on with lost packets?

Oh the lost packets, I mean the UDP protocol itself doesn't guarantee delivery. So if the UDP_send.exe app sends too many keystrokes together, some of the key strokes are lost.

The FPGA verilog I believe pulses the Ethernet every second for packets.
So if I type faster than 1 second per key I should lose keystrokes.

I'm speaking here about the verilog without actually double checking the code, but that is my vague memory of how it appeared to work.

I'll get back to you if I find otherwise.

--- EDITED ---
So it turns out the keystrokes are not lost, the 1 second I was referring to was only for the transmit packets, so it should not be a problem. I'm looking into how to use the UDP module inside another controlling module and extract the data received, so I can use it to control the FPGA.
--- END OF EDIT ---

Thanks for your concern!
Sam

Sam,

I have just started working with fpga's and I am wanting to send udp packets using the spartan 3e XC3S500E to my pc. Could you please direct me to a source where an amature like me can get information regarding this? (tutorials etc.) If you any code that I can go over and understand better that would be great.

Your help in this matter would be highly appretiated.

Fawad

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hi there, I am using Xylo-L board and trying to send packet. Can you kindly explain how you found the Ip address of FPGA and MAC address of FPGA.
I used the netstat -r command at DOS prompt , want to make sure I am following the correct process in finding the Ip of and MAC of FPGA.


tHANKS and really appreciate