hello,
I'm interested in code examples (either language, preferably VHDL) using the Phase Locked Loop with Quartus to produce a precision clock signal that is not a integer division of 33MHz.
Thanks
PLL code examples?
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by dug » Thu Dec 09, 2004 9:00 am
hello dug,
The PLL is easily implemented using the megafunction editor in Quartus II.
A wizard interface gets the user to enter all the functionality parameters of the entity, in this case the PLL. The output includes a code file in the language of the users choosing!
Quartus II is quite impressive.
cheers
The PLL is easily implemented using the megafunction editor in Quartus II.
A wizard interface gets the user to enter all the functionality parameters of the entity, in this case the PLL. The output includes a code file in the language of the users choosing!
Quartus II is quite impressive.
cheers
- dug
- Posts: 2
- Joined: Sun Nov 28, 2004 11:34 pm
by cato » Thu Apr 19, 2007 1:30 am
quick question about quartus PLLS:
I am trying to use the altpll megafunction, but when I compile my code (after putting the megafunction into my design schematic) it says "Total PLLs: 0/1 (0%). "
why does this happen? I don't know what is going wrong.
I am trying to use the altpll megafunction, but when I compile my code (after putting the megafunction into my design schematic) it says "Total PLLs: 0/1 (0%). "
why does this happen? I don't know what is going wrong.
- cato
- Posts: 10
- Joined: Sun Jan 14, 2007 10:49 pm
- Location: michigan (US)
4 posts
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