fpga4fun.com

Hello,

i recevied two Pluto-P boards some days ago and can`t get them working right in my application. I will use them with linuxcnc to drive stepper motors.
Because it didn't work reliable i tried some things with the Pluto-P_StartupKit.zip you receive with the board. I use the EPP2 rbf and the eep.c sample program in an endless loop.
Looking at the verilog file the EPP nWait signal should be just a delayed version of the data and address strobes. But what i measure with the scope looks something like this:

CH1: nAddrStrb
CH2: nDataStrb
CH3: nWrite
CH4: nWait

The board is directly connected to the parallel port with a 5cm (2in) ribbon cable. I tried this with 2 different computers and it looks allways the same.
I have no schematic of the pluto board but there seems to be acircuit between the FPGA and the nWait signal. What is this supposed to do and does the waveform look ok?
I also tried the second barnd new Pluto-P and it looks exactly the same.

Is there a schematic of the Pluto-P available?

thanks you

Michael

Yes, there is a transistor on pin 11 of the parallel port, which inverts the signal from the FPGA and drives the line in open-collector mode. The transistor can drive the line low, and when the transistor if off, we rely on the pull-up resistor on the PC side to drive the line to VCC. If the pull-up in the PC is too low, the signal may go up too slowly. You can try to add an external pull-up if that's a problem (from pin 11 to +3.3V).

The schematic of Pluto-P isn't published, sorry.

Hi,

thanks for your fast response. The pull-up didn't change anything. The problem is discharching the base of the saturated NPN transistor. From the H to L transition on the FPGA pin 87 it takes about 2us until the transistor starts swiching on again. A BAV70 diode parallel to R1 reduced this time to 750ns.

I don't think this will solve the problem i am trying to find but it helps me understand the different timing compared to the FPGA pin.
I still don't understand what the cricuit is good for. Maybe it is used for configuring the FPGA in standard parallel port mode in which nWait is the Busy signal.

Code: Select all

                            4k7     _________ Pin 13 Parallel Port (nWait)
                            R1    |/
FPGA Pin 87 >----------+---###----|  BCW32
                       |          |\
FPGA Pin 90 >-+--###---+            |
              |    R2               GND
              |   4k7
              +------------------------------> Pin 1 parallel port (nWrite)


Scope shots (left is with BAV70; right is original):

CH1: nAddrStrb
CH2: nDataStrb
CH3: FPGA Pin 87
CH4: nWait

Thanks for your help
Michael

You are right about the schematic (although this is for pin 11, not 13) and your assumption.
Another solution to get a faster transistor switching time would be to reduce the resistors value.

I was searching this code for a long time but thanks god I got it...
I appreciate your effort...