fpga4fun.com

Hi,

I just got the Dragon v. J 100K and Flash board ( 2 A/D ).
I run FPGA configuartor and load use USB cable.
It work ok with led samples.
I try the oscilloscope by load
C:\FPGA-AD\Sample files\Dragon 100K Flashy.bit

Then use tool Flash oscilloscope
Use option Flashy J and 100 MHz but cannot any signal.

My signal is 1 dBm connect to one of the BNC input.

Please advice.

Thank

What is the amplitude (in volts)?
Do you get a signal if you just touch the BNC input (Flashy is very sensitive, just touching the input signal will make the trace move).

Hi,

Signal is sine wave and amplitude around 1V.
Touch BNC input see not thing change.
Try both Flashy FPGA versions ( H and and other ) but still
problem. Did the Flashy is implemented the DAC control coding ?

Thanks.

Lan Tran

You're right, I had forgotten to update the startup kit for Flashy rev. J.
Please get it again, I just updated it.

Hi,

After down load the new version it work now.
How I can down load the FPGA code for this oscilloscope?

Thanks.

Lan Tran

Happy to hear that.
The Flashy source code is not public, sorry.

Hi ,

On your web site has a FPGA code for oscilloscope. Did this code really work or just a general idea? If it is good code, what else I need to do so
I can generate bit file-config FPGA and see the signal on oscillosope. ( like ucf file ...)

Following is the copy of the code from your web site.

// Complete design
// Our first working oscilloscope design, isn't that nice?

module oscillo(clk, TxD, clk_flash, data_flash);
input clk;
output TxD;

input clk_flash;
input [7:0] data_flash;

reg [7:0] data_flash_reg; always @(posedge clk_flash) data_flash_reg <= data_flash;

wire [7:0] q_fifo;
fifo myfifo(.data(data_flash_reg), .wrreq(wrreq), .wrclk(clk_flash), .wrfull(wrfull), .wrempty(wrempty), .q(q_fifo), .rdreq(rdreq), .rdclk(clk), .rdempty(rdempty));

// The flash ADC side starts filling the fifo only when it is completely empty,
// and stops when it is full, and then waits until it is completely empty again
reg fillfifo;
always @(posedge clk_flash)
if(~fillfifo)
fillfifo <= wrempty; // start when empty
else
fillfifo <= ~wrfull; // stop when full

assign wrreq = fillfifo;

// the manager side sends when the fifo is not empty
wire TxD_busy;
wire TxD_start = ~TxD_busy & ~rdempty;
assign rdreq = TxD_start;

async_transmitter async_txd(.clk(clk), .TxD(TxD), .TxD_start(TxD_start), .TxD_busy(TxD_busy), .TxD_data(q_fifo));

endmodule

Yes, the code works but is targeted for RS232 (Pluto boards). Also the code lacks some features that have been added after the publication.

Hi,

With dragon board what I need to chage to make the code work for oscilloscope? ( I think USB code instead RS232)and I need the ucf file for the dragon. I can look the circuit diagram and build one from there but cost me time. Can you send me one?

Thank.

Lan Tran

Here's the assignment for the Flashy portion. The USB portion is in the startupkit.

NET "ADC_dataA[0]" LOC = "p86";
NET "ADC_dataA[1]" LOC = "p87";
NET "ADC_dataA[2]" LOC = "p93";
NET "ADC_dataA[3]" LOC = "p95";
NET "ADC_dataA[4]" LOC = "p94";
NET "ADC_dataA[5]" LOC = "p96";
NET "ADC_dataA[6]" LOC = "p99";
NET "ADC_dataA[7]" LOC = "p100";
NET "ADC_dataB[0]" LOC = "p75";
NET "ADC_dataB[1]" LOC = "p76";
NET "ADC_dataB[2]" LOC = "p77";
NET "ADC_dataB[3]" LOC = "p78";
NET "ADC_dataB[4]" LOC = "p79";
NET "ADC_dataB[5]" LOC = "p83";
NET "ADC_dataB[6]" LOC = "p80";
NET "ADC_dataB[7]" LOC = "p84";
NET "clk" LOC = "P18";
NET "clk_ADC" LOC = "p91";
NET "clk_PO" LOC = "p88";
NET "DAC_out" LOC = "p85" ;

Hi,

Thank so lot for information.
On your web, you develop FIFO from Altera.
The dragon board use Xilink. Do you have any advise for this. I use command "coregen" . I choice the Asyn FIFO deep 1023 and 16 bit wide ( 2 A/D each 8 bit ). Please correct if I were wrong.

Thanks.

Tran

You should use a synchronous FIFO (not asynchronous).

Hi Jean,

Thank for the advise.

You have a nice Holiday season

Lan