fpga4fun.com

I read in the spartan data sheet:

"In a bank, inputs requiring VREF can be mixed with those
that do not but only one VREF voltage may be used within a
bank. Input buffers that use VREF are not 5V tolerant.
LVTTL, LVCMOS2, and PCI are 5V tolerant...."

Am I reading that right? No 5v on IO's requiting Vref?

Ive been blasting a few IO Vref pins for quite a while with 5v.Does it really need an attribute in the UCF file for inputs? What about inouts that recieve 5v?


Another thing I noticed is that you can only have clocks on Global clock pins [GCLK]. Am I right?
I never could get a if(clock'event)
or @always() to synthesize on anything but a GCLK pin.


Also on another subject is the IO reads writes with sizes of BYTE WORD and DWORD. the pci controller must have its hands full. if you write a word [16bits] at say $203 then it will shift the least significant byte over to ad[24..31] ,pull low CBE3 IIRC and then It will do another operation at $204 with that most significant byte at ad[7:0]. What I dont understand is why they do all this and still present the full address to the device. You know its $203, just have the word in ad[16:0] and the corresponding CBE pins low so you know its a word operation.Im just more interested as to how a IO operation looks like on the bus coming from the CPU to the PCI controller. How does it know the size of the IO operation? How would a pci controller differ on a NON intel CPU based motherboard?

If a IO operation is not claimed on this ASUS motherboard its sent a total of 4 times. I wonder if its dependent on how many occupied slots there are. I was also saw IO for address $60 and $64 which seems to be the keyboard. what all goes through the PCI bus anyway?



And no, my bios has no auto detect clk/dimm setting but still turns off the clk when it doesnt detect it. I just wish there was someway to have a PnP compatibility with out having PnP;) Windows just seems to think every damn thing needs a driver;) 'new hardware found!' ..So what ,its just a IO port you stupid OS.


just some questions and rants;)

Dragon VCCOs are connected to 3.3V, so pins are ready for LVTTL or LVCMOS 3.3V, and 5V tolerant. I never had to play with VREFs.
You can check the pad report file to see what standard is used on each IO. When the UCF isn't explicit, the default is LVTTL.

You should be able to use other pins than GLCK, but make sure that you route the signal to global lines using BUFGs, and use the global signals as clock.

I'm not sure about PCI, I played with 32 bits aligned accesses only. My understanding is that if you do a CPU 16-bits access at 0x203, the slave won't be able to distinguish it from one CPU 8-bits accesses to 0x203 followed by one at 0x204.
I'm not sure about address 0x60 or 0x64 - probably chipset dependant.
It's unfortunate that some BIOS don't provide the "auto detect clk/dimm" option. I'll have to reflect that into the documentation.

fpga4fun wrote:You should be able to use other pins than GLCK, but make sure that you route the signal to global lines using BUFGs, and use the global signals as clock.

Can you give an example of this? I added BUFG=CLK to the net in the constraint file but still wont synthesize. From what I gathered on the xilinx website that BUFG was only valid for coolrunner cpld's.

Are you still going to be limited to 4 clocks in a design?

Yes, you're still going to be limited to 4 clocks because there are 4 global nets.
On Dragon, one clock pin is hardcoded to 24MHz (USB), one is the socketed oscillator, and two are free.
I never tried to use the BUFG with a non-dedicated clock pin; I'll let you know.

The clock inputs on the Spartan 2 can be connected to almost any output. Lately, I haven't encountered problems connecting clock inputs. I do have issues with error reporting, though. The VHDL synthesizer will sometimes report that I can't use 'X' somewhere without telling me that 'X' is undefined.

Here's an example that works:

Code: Select all

module essai(clk, q);
input clk;
output q;

wire clkI;  IBUF myIBUF(.O(clkI), .I(clk ));
wire clkG;  BUFG myBUFG(.O(clkG), .I(clkI));

reg q;  always @(posedge clkG) q <= ~q;
endmodule

The trick is to use an IBUF followed by a BUFG. Then any non-dedicated input pin can feed one of the 4 global clock nets.
I guess that the drawback of using regular input over dedicated clock pins is that the clock timing might change from one compile to another.